This invention relates to a method of manufacturing a semiconductor device having a CMOSFET, and particularly relates to an improvement in a method of forming a local punch through stopper for preventing short channel effect.
In association with microfabrication of a semiconductor device, the gate length of the transistor is shortened, which causes severe short channel effect. In other words, an electrical characteristic of tile transistor is varied accompanied by dimensional fluctuation of the gate of the MOS transistor.
As a method for preventing the short channel effect, there are known techniques. One is to increase the concentration of impurity doped to the substrate. Another is to provide a region, called punch through stopper, which is more heavily doped than the substrate with an impurity of same polarity type as that of the substrate beneath the channel region. In the former method, junction capacitance between the source/drain region and the substrate is large because of the high impurity concentration of the substrate and the mobility of carrier is lowered because of the high impurity concentration of the channel region. As a result, the electric characteristic of the MOS transistor is lowered. In the latter method, the junction capacitance between the source/drain region and the substrate is increased and the carrier mobility is lowered. In the latter method, the short channel effect is more effectively prevented than the former method, so that the method in which the punch through stopper is provided is often applied to a transistor under about 1.0 micron rule. However, in the MOSFETs, with further short gate length, the electric characteristic is further lowered when the punch through stopper is provided therein.
While, in a CMOS transistor, a p-MOSFET and a n-MOSFET are different from each other in drop of threshold voltage even with the same gate length. For example, FIG. 22 shows variations in threshold voltage of p-MOSFET and n-MOSFET with respect to the gate length in the case of a double well structure ("VLSI manufacturing technique" page 43, edited by Tokuyama and Hashimoto, published by Nikkei BP, Co. Ltd. in 1989). In FIG. 22, it is cleared that even with the same gate length, the threshold voltage of the p-MOSFET drops more severely than that of the n-MOSFET. It is understood that the reason is that impurity immerses to the channel region to shorten an effective channel length in the p-MOSFET more than in the n-MOSFET because the diffusibility of p-type impurity, boron (B), is higher than that of n-type impurity, phosphorus (P) or arsenic (As).
As a method for preventing the short channel effect while preventing the increase in junction capacitance between the source/drain region and the substrate, like the punch through stopper, a method in which a region having the same function as the punch through stopper is formed at a local point is applied to a case with about 1 micron gate length. This method is such that after the gate electrode is patterned, the impurity whose polarity type is the same as that of the substrate is doped more heavily than in the substrate, then the impurity for forming the source/drain regions is implanted. Thereby a narrow region (hereinafter referred to as local punch through stopper) to which the impurity of same polarity type as that of the substrate is more heavily doped than in the channel region is formed.
Laid Open unexamined Japanese Patent Application No.2-22862 discloses an example that the local punch through stopper is formed at the p-MOSFET only. Hereinafter explained is the method of manufacturing this prior art semiconductor device, with reference to FIG.16(a)-16(d) which are sections each showing a state of the semiconductor substrate in the manufacturing method recited in the reference.
First, a n-well 52 is formed in a p-type semiconductor substrate 51, and an isolation 53 is formed at a boundary region thereto and a boundary region to the semiconductor element to separate them. Then, each channel region receives a channel dose 54, and a gate oxide layer 55 is formed entirely. FIG.16(a) shows the state at this time. Next, a polysilicon layer to be a gate electrode is formed, a n-type impurity is introduced to the polysilicon layer to lower the resistance thereof, then the gate electrode 56 is formed by patterning. Subsequently, low-dose phosphorus (P.sup.+) ion implant is conducted entirely to provide n.sup.- regions 59, 59 at regions to be source/drain regions of a n-MOSFET and a p-MOSFET. At the same time, n.sup.- regions 60, 60 to be local punch through stoppers ("n.sup.- pocket region" in the reference) are formed at the p-MOSFET. FIG.16(b) shows the state at this time.
Next, side walls 61 are formed at both sides of the gate electrodes 56 of the n-MOSFET and p-MOSFET. Then, as shown in FIG. 16(c), another protective oxide layer 62 is formed, a resist mask 63 is provided over the p-MOSFET, and high-dose arsenic (As.sup.+) ion implant is conducted to the active region of the n-MOSFET to form source/drain regions 64, 64 of the n-MOSFET. As well, a resist mask 66 is provided over the n-MOSFET, high-dose boron (B.sup.+) ion implant is conducted to provide source/drain regions 65, 65 of the p-MOSFET. FIG. 17(a), 17(b) are respectively sections showing the end parts of the gate electrodes of the n-MOSFET and p-MOSFET which are formed according to the manufacturing method in the reference.
According to the above steps, the n.sup.- regions 59, 59 lightly doped with the n-type impurity serve as LDDs (lightly doped drain) in the n-MOSFET. In other words, the n.sup.- regions 59, 59 restrain the generation of hot carrier in the n-MOSFET where the hot carrier is likely to occur. On the other hand, the n.sup.- regions 60, 60 serve as the local punch through stoppers in the p-MOSFET. Namely, in the p-MOSFET which has the severer short channel effect, the n.sup.- regions 60, 60 restrain the short channel effect.
In the case with the local punch through stoppers, the carrier mobility is not lowered because of no necessity of increasing of impurity concentration of the channel region. Also, the shallow local punch through stopper is formed, which enables to restrain the increase in junction capacitance of the source/drain region to tile substrate. In other words, in the prior art technique in the reference, the impurity for forming local punch through stopper is implanted to the p-MOSFET concurrently with the implantation of impurity for forming LDD of the n-MOSFET, thereby the short channel effect in the p-MOSFET is prevented and durability to hot carrier in the n-MOSFET is improved, while facilitating the manufacturing steps.
However, in the transistor with less than 1 micron gate, the short channel effect is not completely prevented by the above prior art technique. Especially, it is enabled to diffuse the impurity implanted at comparatively low temperature, which causes small difference in diffusibility between boron and phosphorus (or arsenic) at low-temperature diffusion. As a result, for higher integration, the local punch through stopper is required to form not only at the p-MOSFET but also at the n-MOSFET. However, in the above reference, the local punch through stopper cannot be provided at the n-MOSFET. Therefore, the short channel effect could not be effectively prevented in the CMOSFET with less than 1.0 micron gate.
Moreover, since the inclination of distribution of impurity concentration in the source/drain regions of the p-MOSFET becomes sever in association with the lowering of the diffusion temperature of B.sup.+ ion, the durability to hot carrier is lowered also in the p-MOSFET. Therefore, in the manufacturing method in the above reference, in spite of the side walls provided, the durability to hot carrier in the p-MOSFET may be lowered without the LDD in the p-MOSFET.
In order to completely prevent the short channel effect in the CMOSFET having further micro gate, the punch through stoppers are required to be formed at both n-MOSFET and p-MOSFET. Therefore, in general, the local punch through shoppers are formed at both n-MOSFET and p-MOSFET according to the steps shown in FIGS. 18(a)-18(f) and 21. Hereinafter discussed is a method of manufacturing a semiconductor device having the conventional local punch through stoppers, with reference to the sections of FIG. 18(a)-18(f) and the flow chart of FIG.21.
First, after the n-well 52 at the p-type semiconductor substrate 51 and the isolation 53 are formed, steps CX1 and CX2 in FIG.21 are conducted to form the gate oxide layer 55 and the polysilicon layer, whereby the semiconductor substrate shown in FIG. 18(a) is obtained. The steps insofar are the same as that in the above reference (refer to FIG. 16 (a)). Next, as shown in FIG. 18(b), after introducing the n-type impurity into the polysilicon layer, step CX3 is conducted to form the gate electrode 56 by patterning the polysilicon layer. After a protective oxide layer is formed by conducting a protective oxidation step of CX4, the resist mask 67 is formed, a part of p-MOSFET is opened, low-dose phosphorus (P.sup.+) ion implant is conducted to form the n.sup.- regions 71, 71 to be the local punch through stoppers at the p-MOSFET and the resist mask 67 is removed in steps CX5-CX8.
Next, as shown in FIG. 18(c), in steps CX9 to CX11, the resist mask 68 is provided over the p-MOSFET, the upper part of the n-MOSFET is opened, and low-dose B.sup.+ or BF2.sup.+ ion implant is conducted to form p.sup.- regions 72, 72 to be the local punch through stoppers at the n-MOSFET. Thereafter, as shown in FIG. 18(d), at steps CX12 and CX13, low-dose P.sup.+ ion implant is conducted to form n.sup.- regions 73, 73 to be LDDs of the n-MOSFET and the resist mask 68 is removed.
Subsequently, annealing is conducted at step CX14, and the side walls 61, the protective oxide layer 62 and the resist mask 69 are formed in steps CX15-CX18. At step CX19, high-dose As.sup.+ ion implant is conducted to the n-MOSFET to form the source/drain regions 74, 74 (refer to FIG. 18(e)). Then, the resist mask 69 is removed at step CX20. The resist mask 70 open to only the p-MOSFET is formed and high-dose As.sup.+ ion implant is conducted to form the source/drain regions 75, 75 of the p-MOSFET in steps CX21 and CX22 (refer to FIG. 18(f)). Finally, the resist mask 70 is removed at step CX24.
FIGS. 19(a), 19(b) show respective sectional constructions of the end parts of the gate electrodes of the respective MOSFETs formed according to the above method. As understood from FIGS. 19(a), 19(b), in addition to the source/drain region 74 heavily doped with the impurity and the LDD 73 lightly doped with the impurity, the local punch through stopper 72 doped with the impurity of opposite polarity type thereto is formed in the n-MOSFET. Also, the source/drain region 75 heavily doped with the impurity and the local punch through stopper 71 lightly doped with the impurity of opposite polarity type thereto are formed in the p-MOSFET. Accordingly, compared with the structure formed according to the prior art method in the reference (see FIG. 17), the short channel effect in the n-MOSFET is prevented and the generation of hot carrier is also lowered. In a case where the LDD is formed at the p-MOSFET, low-dose B.sup.+ ion implant is conducted after the step CX7.
Moreover, FIG. 20 shows the steps up to the formation of the gate oxide layer. In detail, after formation of the well and the isolation, the protective oxide layer is formed at CY1, the resist is coated and the resist mask open to only the upper part of the n-MOSFET is formed in steps CY2, CY3. Then, the BF2.sup.+ ion which is an impurity for controlling threshold value in the n-MOSFET is implanted at step CY4, and the resist mask is removed at CY5. As well, the coating of resist, the formation of resist mask, the implantation of P.sup.+ ion for controlling threshold value and the removal of resist mask are conducted in steps CY6-CY1O for the p-MOSFET. Then, at step CY11, the protective oxide layer is removed. Thereafter, another gate oxide layer is formed at the above step CX1, and the step CX2 and the following steps thereafter are conducted.
However, in the above conventional method shown in FIGS.18(a)-18(f) and FIG. 21, the formation of resist mask is required four times, which increases the manufacturing cost and the defect occurring rate. It is considered to omit some steps of the method by using the technique in the above reference. For example, at the step CX7, the low-dose P.sup.+ ion implant is conducted also to the n-MOSFET without using the resist mask 67 to thus form the LDD of the n-MOSFET. As a result, one step of forming the resist mask can be omitted. However, there still remains three resist mask forming steps, which means increased resist mask forming steps, compared with the manufacturing method of the CMOSFET without the local punch through stopper.